The present invention is related to wafer processing and in particular to a method of etching a metal layer to form interconnect structures in integrated circuits (IC). More specifically, the present invention relates to a method of using a hard mask deposited by a chemical vapor deposition process as a pattern mask for etching copper-based interconnect structures.
For the past few decades, chip makers have etched aluminum circuits on silicon wafers. However, the ever shrinking universe of integrated circuits has made the use of aluminum as an interconnect structure problematic. Accordingly, much of the industry is switching to copper for conduction lines in circuits having minimum feature sizes of 0.2 micron or less. Copper has less resistance than aluminum, and therefore transmits electrical signals faster. More specifically, copper wires conduct electricity with about 40 percent less resistance than aluminum. This translates into a speed up of as much as 15 percent in microprocessors that contain copper wires. Copper wires are also less vulnerable than those made of aluminum to electromigration, the movement of individual atoms through a wire caused by high electric currents. In addition, the widths of copper wires can be squeezed down to the 0.2 micron range and below from the current widths—a reduction far more difficult for aluminum.
Several different copper integration options are being pursued by semiconductor manufacturers. Among these are the “Damascene” and the subtractive etch approaches. While many have adopted a damascene-based process as a method of depositing copper interconnects onto silicon, others are developing methods to etch copper interconnects onto a substrate. Damascene-based local on-chip interconnections have been used since the late 1980s and have since gained popularity in the semiconductor manufacturing industry. Currently, the damascene method appears to be the more commercially feasible method of fabricating submicron copper-based interconnections, primarily because of the difficulty of etching copper at these levels.
One problem with etching copper is the requirement for an elevated temperature etch (e.g., higher than 200° C.). The need for an elevated temperature etch is in turn driven by the insufficient volatilization of copper etch products at low temperatures (e.g., lower than 200° C.). Additionally, the need for an elevated temperature etch is driven by a need to etch copper at high etch rates (e.g., 5000 Å/min). Therefore, in order to rapidly etch copper, sufficient volatilization of copper etch products is required, which is achieved by increasing the wafer temperature during copper etching. However, typical masks made from conventional photoresist materials will break down at temperatures higher than 200° C., and thus are not suitable for use as masks for the etching of copper. There is therefore a need for a high temperature mask for copper etch; a mask that is stable at the elevated temperatures needed to etch copper at rates high enough for commercially viable semiconductor manufacturing. Besides the temperature stability issues described above, it is known that typical photoresist layers deposited by spin-on methods have layer thickness uniformity problems, with the uniformity problems being more pronounced for thinner layers (e.g., less than 8000 Å). So, besides needing a mask material that is stable at high temperatures, such a mask needs to avoid the layer thickness uniformity problems associated with typical spin-on deposited photoresist materials.
Copper etching is typically carried out using chlorine-based chemistries. Typical photoresist materials have a low etch selectivity with respect to the metal being etched using chlorine-based chemistries, thus requiring rather thick layers of the photoresist materials. It is preferred to use a mask material having a higher etch selectivity with respect to the metal being etched. For example, the etch selectivity for conventional photoresist with respect to copper is 2:1, while a preferred etch selectivity should be at least greater than 3:1. Some research institutions have investigated the reactive ion etching of copper in chlorine-based plasmas using SiO2 or Si3N4 (commonly abbreviated as SiN) hard masks. The results of these investigations show that copper dry etching using SiO2 and SiN hard masks is possible at substrate temperatures as low as 165° C. However, the etch selectivity of copper with respect to SiO2 and SiN is generally considered to be too low for the process to be efficient in a commercial setting. Furthermore, SiO2 and SiN masks are also generally considered to be difficult to remove after copper etching. SiO2 and SiN masks are difficult to remove, because their removal generally requires using strong chemicals and strong physical bombardments, that also could damage the underlying layers (e.g. copper layer).
A fluorinated amorphous carbon film having both thermal stability and a low dielectric constant has been developed by the assignee herein for use as a low k dielectric material, and is described in a pending U.S. patent application Ser. No. 08/948,799, filed Oct. 10, 1997, entitled “Method of Depositing an Amorphous Fluorocarbon Film Using HDP-CVD.” While this film has the requisite thermal stability for use a pattern mask for etching of metals, its use for such a purpose was not previously contemplated. This is because previous methods involved the etching of aluminum which happens at temperatures below 100° C., and thus a high temperature mask was not needed. Moreover, while an amorphous fluorinated carbon film has the requisite thermal stability, its etch rate using a chlorine-based plasma etch process is also too high with respect to the underlying metal, and thus results in an etch selectivity which is too low for the process to be viable.
A type of amorphous carbon (a-C) film that has attracted interest because of its unique diamond like characteristics is the so-called diamond like carbon (DLC) film. While the DLC film is similar to the amorphous fluorinated carbon (a-FC) film described above, and while it may have a better etch selectivity than the a-FC film, its deposition occurs at temperatures in excess of 800° C., which is higher than the commonly accepted 450° C. substrate temperature threshold for typical semiconductor processing.
There is therefore a need for a feasible method of fabricating copper-based interconnections based on etching copper at the submicron level. More particularly, there is a need for a pattern mask for etching of copper, that can be deposited thinly and uniformly, while maintaining the wafer's temperature below 450° C.; a mask that is thermally stable at the elevated temperatures needed for copper etching, and one that provides for a high etch selectivity with respect to the underlying metal.